{"V(OL)Max.(V)Lo Level Out.Volt.":".33","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Pins":"N\/A","@Iol (A)":"6m","Logic Level Family":"CMOS and T","Package Body Material":"Ceramic","Gate Capacity":"6000","VIL Max. (TTL) (V)":".8","Package":"QFP","VIH Min. (TTL) (V)":"2","@IOH (test)":"6m","Configurable Logic Blocks":"848","Military":"N","Number of User I\/Os":"168","V(OH)Min.(V)Hi Level Out.Volt.":"3.84","Vsup (+) Maximum (V)":"7","JEDEC Std 30 Outline Code":"S-CPGA-P","Technology":...

{"Category":"Integrated Circuits (ICs)","PCN Obsolescence\/ EOL":"Multiple Devices 01\/Aug\/2014","Number of LABs\/CLBs":"848","Mounting Type":"Through Hole","Family":"Embedded - FPGAs (Field Programmable Gate Array)","Number of Logic Elements\/Cells":"-","Series":"ACT\u2122 3","Standard Package":"10","Supplier Device Package":"207-CPGA (44.96x44.96)","Datasheets":"ACT 3 Family","Total RAM Bits":"-","Number of Gates":"6000","Operating Temperature":"0\u00b0C ~ 70\u00b0C","Voltage - Supply":"4.5 V ~ 5.5 V","P...